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The UT Department of Computer Sciences is pleased to announce its annual Visions Lecture, the latest in a series of lectures by UTCS faculty who have been recognized by their community for notable achievements in research, teaching or service.
This year's lecture will take place on Monday, November 9, 2009 from 4:15 - 5:30 p.m. in the Avaya Auditorium, ACES 2.302. Private reception by invitation only following the lectures.
James C. Browne
"Looking Forward by Looking Back"
Talk Abstract:
This talk will consider possible futures for computer science based on examining the fifty years I have been a participant the use of computers and their role in science, engineering, industry and social and cultural life. The perspective will be Computer Science at UT-Austin. The questions to be considered include: How will the discipline of computer science evolve, particularly at UT-Austin? How will computer science interact with the scientific, business and cultural worlds? The answers to be suggested include unresolved issues which the audience will be asked to consider.
Alan Kaylor Cline
"Socrates, Moore, and Computer Science Education"
Talk Abstract:
The Socratic Method, the R. L. Moore Method, and Discovery Learning are three forms of instruction that endeavor to produce deep understanding through a maximum of student participation. The Moore method in which students develop theory based on a small set of axioms and carefully constructed problems has gained world-wide acceptance from its practice on our campus. My own exposure to the method was a functional analysis course taught by Paul Halmos. Halmos later said “The Moore method is, I am convinced the right way to teach anything and everything.”
I will begin by describing how – in both positive and negative respects –Halmos’s course was life-changing for me. Then I’All present my thoughts on the Halmos claim: in particular is the Moore method the appropriate approach for computer science instruction.
Jayadev Misra
"Should We Teach Formal Methods at All?"
Talk Abstract:
I have devoted most of my career to research on applications of formal methods in Computer Science. Yet, it is not clear to me how much (or, even, whether) to teach formal methods, particularly to undergraduates. How much of their routine activities, including programming, depends on formal methods? Would it be simpler to replace formal reasoning by appeal to intuition and well-chosen examples, a path almost universally taken at other schools? UT has a proud tradition of research in formal methods. Can we leverage that in teaching? Then would we blaze a new path, or just have disgruntled students?
I will draw upon my experience with undergraduates, formal methods and "computational thinking" to illustrate the problems, pit falls and the opportunities.�
Sign-up schedule for this talk can be found at http://www.cs.utexas.edu/department/webevent/utcs/events/cgi/list_events.cgi
Type of Talk: UTCS Colloquium
Speaker/Affiliation: Geoffrey Challen/Harvard University
Date/Time: Friday, November 13, 2009/ 1:00 p.m. until 2:30 p.m.
Location: ACES 2.402
Host: Mike Dahlin
Title: "Managing Sensor Network Resource Usage and Monitoring Active Volcanoes"
Talk Abstract:
Sensor networks composed of large numbers of self-organizing embedded devices are an increasingly valuable tool for understanding our world. Deployed networks allow scientists to observe phenomena at a scale and resolution that challenge existing instrumentation. Some call this new instrument the macroscope.
My project uses sensor networks to monitor active volcanoes. Due to the high data rates and stringent fidelity requirements of this application, providing output suitable for scientific analysis requires carefully directing the limited resources available at each node. In this talk I will present Lance, a general approach to bandwidth and energy management targeting reliable data collection for sensor networks.
By combining an application-level determination of value with a system-level estimation of cost, Lance maximizes the value of the data returned to the application by optimally allocating bandwidth and energy devoted to signal collection. Lance's design decouples data collection policy from mechanism, allowing its optimization metrics to be customized to suit a variety of application goals. I will motivate and describe the Lance architecture, present results from the lab and the field, and discuss continuing efforts in this area, including single-node and network-wide architectures for distributed energy management.
Speaker Bio:
Geoffrey Challen (né Werner-Allen) is a Ph.D. Candidate in Computer Science at the Harvard University School of Engineering and Applied Sciences, advised by Matt Welsh. His research addresses the systems and networking challenges necessary to enable high-fidelity sensing applications, focusing specifically on maximizing the usage of the limited resources available to sensor network nodes. Working with geoscientists, he has helped perform three sensor network deployments on active Ecuadorean volcanoes. He built and maintains MoteLab, a wireless sensor network testbed used by researchers worldwide, and is a co-editor of a forthcoming book on sensor network deployments. Geoffrey is a 2009 Siebel Fellow, and a Resident Tutor at Eliot House.
Revelant URL:
http://www.eecs.harvard.edu/~werner/
There is a sign-up schedule for this talk that can be found at http://www.cs.utexas.edu/department/webevent/utcs/events/cgi/list_events.cgi
Type of Talk: UTCS Colloquium/Architecture
Speaker/ Affiliation: Satish Narayanasamy/ University of Michigan
Date/Time: Monday, October 26, 2009/ 3:30 p.m. until 5:00 p.m.
Location: ACES 2.402
Host: Emmett Witchel
Talk Title: "A Case Against Unbridled Parallelism"
Talk Abstract:
The fundamental problem with shared-memory multi-threaded programming model is that it exposes an unbounded number of thread interleavings to the parallel runtime system. Current testing methods focus on stress testing, which try to expose as many different thread interleavings as possible. But, it remains impractical for programmers to test and ensure the correctness of all possible thread interleavings.
I will first argue that instead of investing more and more effort on stress testing, we should develop runtime mechanisms that would constrain the thread interleaving during a production run to avoid untested interleavings, which I will show could reduce the chance of triggering a concurrency bug significantly. I will discuss techniques for encoding tested interleavings in a program's binary, and hardware support for efficiently enforcing those constraints in production runs.
I will also talk about deterministic replay, which could help programmers understand and debug a multi-threaded program execution by allowing them to reproduce the thread interleaving seen during an execution. Prior software techniques incur more than 10x runtime performance overhead, but I will discuss a speculative recording technique that enabled us to build a software record-and-replay system that incurs only about 30-50% overhead.
Speaker Bio:
Satish Narayanasamy is an Assistant Professor in the EECS Department at the University of Michigan. He has a Ph.D. in Computer Science from the University of California, San Diego. His research interests include computer architecture, hardware mechanisms and software tools for programming many-cores, and system reliability. He has received two IEEE Top Picks awards.
Type of Talk: UTCS Colloquium/ Architecture
Speaker/ Affiliation: Mark Horowitz/ Stanford University
Date/Time: Monday, November 2, 2009/ 11:00 a.m.
Location: ACES 6.304
Host: Steve Keckler
Talk Title: "Why Design Must Change: Rethinking Digital Design"
Talk Abstract:
In the mid 1980's the power growth that accompanied scaling forced the industry to focus on CMOS technology, and leave nMOS and bipolars for niche applications. Twenty years later, CMOS technology is facing power issues of its own. After first reviewing the "cause" of the problem, it will become clear that there are not easy solutions this time -- no new technology or simple system/circuit change will rescue us. Power, and not number of devices is now the primary limiter of chip performance, and the need to create power efficient designs is changing how we do design. In the past this we would turn to specialized computation (ASICs) to create the needed efficiency, but the rising NRE costs for chip design (now over $10M/chip) has caused the number of ASIC design starts to fall not rise.
To get out of this paradox, we need to change the way we think about chip design. For many reasons I don't believe that either the current SoC, or high-level language effort will solve this problem. Instead, we should acknowledge that working out the interactions in a complex design is complex, and will cost a lot of money, even when we do it well. So once we have worked it out, we want to leverage this over solution over a broader class of chips. We can accomplish this by creating a "fixed" system architecture, but of very flexible components. That is instead of building a programmable chip to meet
a broad class of application needs, you create a virtual programmable chip, that is MUCH more flexible than any real chip. The application designer (the new chip designer) will then configure this substrate to optimize for their application and then create that chip. To demonstrate how this might work, we use a multiprocessor generator to create an customized CMP which executes H.264 encode with an energy efficiency comparable to an ASIC. As we show in this example for very low energy computation, DRAM energy can be any issue, and we will end the talk describing how to address this final energy frontier.
Speaker Bio:
Mark Horowitz is the Chair of the Electrical Engineering Department and the Yahoo! Founders Professor of the School of Engineering at Stanford University. In addition he is Chief Scientist at Rambus Inc. He received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Dr. Horowitz has received many awards including a 1985 Presidential Young Investigator Award, the 1993 ISSCC Best Paper Award, the ISCA 2004 Most Influential Paper of 1989, and the 2006 Don Pederson IEEE Technical Field Award. He is a fellow of IEEE and ACM and is a member of the National Academy of Engineering and the American Academy of Arts and Science.
Dr. Horowitz's research interests are quite broad and span using EE and CS analysis methods to problems in molecular biology to creating new design methodologies for analog and digital VLSI circuits. He has worked on many processor designs, from early RISC chips to creating some of the first distributed shared memory multiprocessors, and is currently working on on-chip multiprocessor designs. Recently he has worked on a number of problems in computational photograph. In 1990, he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology, and has continued work in high-speed I/O at Stanford. His current research includes multiprocessor design, low power circuits, high-speed links,
computational photography, and applying engineering to biology.
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The Computer Architecture Seminar Series is sponsored jointly by the
Departments of Computer Science and Electrical & Computer Engineering
and is supported by a grant from IBM.
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Scalable Yahoo Map of 24th & Speedway:
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Parking for off-campus visitors: We suggest that you park in the San Jacinto
parking garage (formerly PG1) at 24th & San Jacinto. Parking validation will
be available. Please contact the host for this seminar or stop by the
refreshment cart to have your parking validated.
Submap including San Jacinto Parking Garage:
http://www.utexas.edu/maps/main/areas/law.html
Submap including ACES: http://www.utexas.edu/maps/main/areas/eastmall.html
Please contact Gem Naivar at gem@cs.utexas.edu if you need any further
information to attend the seminar.
Type of Talk: UTCS Colloquium
Speaker/ Affiliation: Arvind Narayanan/ Stanford University
Date/Time: Thursday, November 5, 2009/ 11:00 a.m.
Location: ACES 2.402
Host: Vitaly Shmatikov
Talk Title: "What does it mean to own our genes?"
Talk Abstract:
Given that each of us shares genetic material with our blood
relatives, to what extent can one expect to keep one's genetic
information private? I will consider this question with respect to an
attacker equipped with large-scale (albeit incomplete and "noisy")
information about the blood relationships in a large population group,
i.e., a genealogical graph.
Given this kind of auxiliary information, it turns out that the
availability of genotype information of a small fraction of
individuals -- as little as 0.2%, in preliminary experiments -- is
enough to cause the majority of the population to lose any hope of
genetic privacy. I will describe a strong inference attack that allows
the attacker to re-identify completely anonymous genetic material,
such as pieces of hair collected en masse from public spaces without
the consent or even the knowledge of the potential victims.
There are many ongoing efforts aimed at aggregating genealogical data
on a massive scale. As I will show, the compilation of the "world's
family tree" is a matter of time. Further, there are several
population groups for which enough auxiliary data is already available
to leave them vulnerable to genetic re-identification.
There is no purely technological fix to this attack. I will briefly
present policy prescriptions that may delay ubiquitous genetic
re-identifiability, and argue that genetic privacy norms must change
to accommodate the new technological reality.
Speaker Bio:
Arvind Narayanan is a post-doctoral researcher at Stanford. He
recently finished his Ph.D at the University of Texas at Austin,
advised by Vitaly Shmatikov. His research is on the privacy and
anonymity issues involved in publishing large-scale datasets about
people. His thesis, in a sentence, is that the level of anonymity that
society expects - and companies claim to provide - in published databases is fundamentally unrealizable. He blogs about his anonymity-breaking efforts and other research at http://33bits.org/